{"id":4568,"date":"2024-01-26T12:45:44","date_gmt":"2024-01-26T11:45:44","guid":{"rendered":"https:\/\/www.heinpragt.nl\/?p=4568"},"modified":"2024-01-26T12:49:09","modified_gmt":"2024-01-26T11:49:09","slug":"ttl-ic-overview-2","status":"publish","type":"post","link":"https:\/\/www.heinpragt.nl\/?p=4568","title":{"rendered":"TTL IC Overview"},"content":{"rendered":"\n<p>This is a table with an overview of all TTL IC typenumbers and a short description of the chip. The chips are available in many variants such as LS and HC types, the operation is the same, but the electrical specifications are different. You cannot simply replace an LS with an HC type without being sure that the fan-in and fan-out and the threshold values \u200b\u200bhave no effect.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">List of TTL IC&#8217;s<\/h3>\n\n\n\n<style>table td { border: 1px solid;} table th { border: 2px solid black; background-color: #d0d0d0; }<\/style>\n<table>\n<tr><td><tr><th>Part number<\/th><th>\tDescription<\/th><\/tr>\n<tr><td>7400\t<\/td><td>\tquad 2-input\u00a0NAND gate<\/td><\/tr>\n<tr><td>7401\t<\/td><td>\tquad 2-input NAND gate with\u00a0open collector\u00a0outputs<\/td><\/tr>\n<tr><td>7402\t<\/td><td>\tquad 2-input\u00a0NOR\u00a0gate<\/td><\/tr>\n<tr><td>7403\t<\/td><td>\tquad 2-input NAND gate with open collector outputs<\/td><\/tr>\n<tr><td>7404\t<\/td><td>\thex\u00a0inverter<\/td><\/tr>\n<tr><td>7405\t<\/td><td>\thex inverter with open collector outputs<\/td><\/tr>\n<tr><td>7406\t<\/td><td>\thex inverter buffer\/driver with 30\u00a0V open collector outputs<\/td><\/tr>\n<tr><td>7407\t<\/td><td>\thex buffer\/driver with 30\u00a0V open collector outputs<\/td><\/tr>\n<tr><td>7408\t<\/td><td>\tquad 2-input\u00a0AND gate<\/td><\/tr>\n<tr><td>7409\t<\/td><td>\tquad 2-input AND gate with open collector outputs<\/td><\/tr>\n<tr><td>7410\t<\/td><td>\ttriple 3-input NAND gate<\/td><\/tr>\n<tr><td>7411\t<\/td><td>\ttriple 3-input AND gate<\/td><\/tr>\n<tr><td>7412\t<\/td><td>\ttriple 3-input NAND gate with open collector outputs<\/td><\/tr>\n<tr><td>7413\t<\/td><td>\tdual\u00a0Schmitt trigger\u00a04-input NAND gate<\/td><\/tr>\n<tr><td>7414\t<\/td><td>\thex Schmitt trigger inverter<\/td><\/tr>\n<tr><td>7415\t<\/td><td>\ttriple 3-input AND gate with open collector outputs<\/td><\/tr>\n<tr><td>7416\t<\/td><td>\thex inverter buffer\/driver with 15\u00a0V open collector outputs<\/td><\/tr>\n<tr><td>7417\t<\/td><td>\thex buffer\/driver with 15\u00a0V open collector outputs<\/td><\/tr>\n<tr><td>7418\t<\/td><td>\tdual 4-input NAND gate with Schmitt trigger inputs<\/td><\/tr>\n<tr><td>7419\t<\/td><td>\thex Schmitt trigger inverter<\/td><\/tr>\n<tr><td>7420\t<\/td><td>\tdual 4-input NAND gate<\/td><\/tr>\n<tr><td>7421\t<\/td><td>\tdual 4-input AND gate<\/td><\/tr>\n<tr><td>7422\t<\/td><td>\tdual 4-input NAND gate with open collector outputs<\/td><\/tr>\n<tr><td>7423\t<\/td><td>\texpandable dual 4-input NOR gate with strobe<\/td><\/tr>\n<tr><td>7424\t<\/td><td>\tquad 2-input NAND gate gates with schmitt-trigger line-receiver inputs.<\/td><\/tr>\n<tr><td>7425\t<\/td><td>\tdual 4-input NOR gate with strobe<\/td><\/tr>\n<tr><td>7426\t<\/td><td>\tquad 2-input NAND gate with 15\u00a0V open collector outputs<\/td><\/tr>\n<tr><td>7427\t<\/td><td>\ttriple 3-input NOR gate<\/td><\/tr>\n<tr><td>7428\t<\/td><td>\tquad 2-input NOR buffer<\/td><\/tr>\n<tr><td>7430\t<\/td><td>\t8-input NAND gate<\/td><\/tr>\n<tr><td>7431\t<\/td><td>\thex delay elements<\/td><\/tr>\n<tr><td>7432\t<\/td><td>\tquad 2-input\u00a0OR gate<\/td><\/tr>\n<tr><td>7433\t<\/td><td>\tquad 2-input NOR buffer with open collector outputs<\/td><\/tr>\n<tr><td>7434\t<\/td><td>\thex noninverters<\/td><\/tr>\n<tr><td>7435\t<\/td><td>\thex noninverters with open-collector outputs<\/td><\/tr>\n<tr><td>7436\t<\/td><td>\tquad 2-input NOR gate (different\u00a0pinout\u00a0than 7402)<\/td><\/tr>\n<tr><td>7437\t<\/td><td>\tquad 2-input NAND buffer<\/td><\/tr>\n<tr><td>7438\t<\/td><td>\tquad 2-input NAND buffer with open collector outputs<\/td><\/tr>\n<tr><td>7439\t<\/td><td>\tquad 2-input NAND buffer with open collector outputs, input and output terminals flipped, otherwise functionally identical to 7438<\/td><\/tr>\n<tr><td>7440\t<\/td><td>\tdual 4-input NAND buffer<\/td><\/tr>\n<tr><td>7441\t<\/td><td>\tBCD\u00a0to decimal\u00a0decoder\/Nixie tube\u00a0driver<\/td><\/tr>\n<tr><td>7442\t<\/td><td>\tBCD to decimal decoder<\/td><\/tr>\n<tr><td>7443\t<\/td><td>\texcess-3\u00a0to decimal decoder<\/td><\/tr>\n<tr><td>7444\t<\/td><td>\texcess-3-Gray code\u00a0to decimal decoder<\/td><\/tr>\n<tr><td>7445\t<\/td><td>\tBCD to decimal decoder\/driver<\/td><\/tr>\n<tr><td>7446\t<\/td><td>\tBCD to\u00a0seven-segment display\u00a0decoder\/driver with 30\u00a0V open collector outputs<\/td><\/tr>\n<tr><td>7447\t<\/td><td>\tBCD to 7-segment decoder\/driver with 15\u00a0V open collector outputs<\/td><\/tr>\n<tr><td>7448\t<\/td><td>\tBCD to 7-segment decoder\/driver with Internal Pullups<\/td><\/tr>\n<tr><td>7449\t<\/td><td>\tBCD to 7-segment decoder\/driver with open collector outputs<\/td><\/tr>\n<tr><td>7450\t<\/td><td>\tdual 2-wide 2-input AND-OR-invert gate (one gate expandable)<\/td><\/tr>\n<tr><td>7451\t<\/td><td>\tdual 2-wide 2-input AND-OR-invert gate<\/td><\/tr>\n<tr><td>7452\t<\/td><td>\texpandable 4-wide 2-input AND-OR gate<\/td><\/tr>\n<tr><td>7453\t<\/td><td>\texpandable 4-wide 2-input AND-OR-invert gate<\/td><\/tr>\n<tr><td>7454\t<\/td><td>\t3-2-2-3-input AND-OR-invert gate<\/td><\/tr>\n<tr><td>7455\t<\/td><td>\t2-wide 4-input AND-OR-invert Gate (74H version is expandable)<\/td><\/tr>\n<tr><td>7456\t<\/td><td>\t50:1\u00a0frequency divider<\/td><\/tr>\n<tr><td>7457\t<\/td><td>\t60:1 frequency divider<\/td><\/tr>\n<tr><td>7458\t<\/td><td>\t2-input &#038; 3-input AND-OR Gate<\/td><\/tr>\n<tr><td>7459\t<\/td><td>\t2-input &#038; 3-input AND-OR-invert Gate<\/td><\/tr>\n<tr><td>7460\t<\/td><td>\tdual 4-input expander<\/td><\/tr>\n<tr><td>7461\t<\/td><td>\ttriple 3-input expander<\/td><\/tr>\n<tr><td>7462\t<\/td><td>\t3-2-2-3-input AND-OR expander<\/td><\/tr>\n<tr><td>7463\t<\/td><td>\thex current sensing interface gates<\/td><\/tr>\n<tr><td>7464\t<\/td><td>\t4-2-3-2-input AND-OR-invert gate<\/td><\/tr>\n<tr><td>7465\t<\/td><td>\t4-2-3-2 input AND-OR-invert gate with open collector output<\/td><\/tr>\n<tr><td>7468\t<\/td><td>\tdual 4 bit decade counters<\/td><\/tr>\n<tr><td>7469\t<\/td><td>\tdual 4 bit binary counters<\/td><\/tr>\n<tr><td>7470\t<\/td><td>\tAND-gated positive edge triggered J-K\u00a0flip-flop\u00a0with preset and clear<\/td><\/tr>\n<tr><td>7471\t<\/td><td>\tAND-or-gated J-K master-slave flip-flop with preset<\/td><\/tr>\n<tr><td>7472\t<\/td><td>\tAND gated J-K master-slave flip-flop with preset and clear<\/td><\/tr>\n<tr><td>7473\t<\/td><td>\tdual J-K flip-flop with clear<\/td><\/tr>\n<tr><td>7474\t<\/td><td>\tdual D positive edge triggered flip-flop with preset and clear<\/td><\/tr>\n<tr><td>7475\t<\/td><td>\t4-bit bistable\u00a0latch<\/td><\/tr>\n<tr><td>7476\t<\/td><td>\tdual J-K flip-flop with preset and clear<\/td><\/tr>\n<tr><td>7477\t<\/td><td>\t4-bit bistable latch<\/td><\/tr>\n<tr><td>7478\t<\/td><td>\tdual positive pulse triggered J-K flip-flop with preset, common clock, and common clear<\/td><\/tr>\n<tr><td>7479\t<\/td><td>\tdual D flip-flop<\/td><\/tr>\n<tr><td>7480\t<\/td><td>\tgated\u00a0full adder<\/td><\/tr>\n<tr><td>7481\t<\/td><td>\t16-bit\u00a0random access memory<\/td><\/tr>\n<tr><td>7482\t<\/td><td>\t2-bit binary full adder<\/td><\/tr>\n<tr><td>7483\t<\/td><td>\t4-bit binary full adder<\/td><\/tr>\n<tr><td>7484\t<\/td><td>\t16-bit\u00a0random access memory<\/td><\/tr>\n<tr><td>7485\t<\/td><td>\t4-bit\u00a0magnitude comparator<\/td><\/tr>\n<tr><td>7486\t<\/td><td>\tquad 2-input\u00a0XOR gate<\/td><\/tr>\n<tr><td>7487\t<\/td><td>\t4-bit true\/complement\/zero\/one element<\/td><\/tr>\n<tr><td>7488\t<\/td><td>\t256-bit\u00a0read-only memory<\/td><\/tr>\n<tr><td>7489\t<\/td><td>\t64-bit random access memory<\/td><\/tr>\n<tr><td>7490\t<\/td><td>\tdecade counter\u00a0(separate divide-by-2 and divide-by-5 sections)<\/td><\/tr>\n<tr><td>7491\t<\/td><td>\t8-bit\u00a0shift register, serial In, serial out, gated input<\/td><\/tr>\n<tr><td>7492\t<\/td><td>\tdivide-by-12 counter (separate divide-by-2 and divide-by-6 sections)<\/td><\/tr>\n<tr><td>7493\t<\/td><td>\t4-bit binary counter (separate divide-by-2 and divide-by-8 sections)<\/td><\/tr>\n<tr><td>7494\t<\/td><td>\t4-bit shift register, dual asynchronous presets<\/td><\/tr>\n<tr><td>7495\t<\/td><td>\t4-bit shift register, parallel In, parallel out, serial input<\/td><\/tr>\n<tr><td>7496\t<\/td><td>\t5-bit parallel-In\/parallel-out shift register, asynchronous preset<\/td><\/tr>\n<tr><td>7497\t<\/td><td>\tsynchronous 6-bit binary rate multiplier<\/td><\/tr>\n<tr><td>7498\t<\/td><td>\t4-bit data selector\/storage register<\/td><\/tr>\n<tr><td>7499\t<\/td><td>\t4-bit bidirectional universal shift register<\/td><\/tr>\n<tr><td>74100\t<\/td><td>\tdual 4-bit bistable latch<\/td><\/tr>\n<tr><td>74101\t<\/td><td>\tAND-OR-gated J-K negative-edge-triggered flip-flop with preset<\/td><\/tr>\n<tr><td>74102\t<\/td><td>\tAND-gated J-K negative-edge-triggered flip-flop with preset and clear<\/td><\/tr>\n<tr><td>74103\t<\/td><td>\tdual J-K negative-edge-triggered flip-flop with clear<\/td><\/tr>\n<tr><td>74104\t<\/td><td>\tJ-K master-slave flip-flop<\/td><\/tr>\n<tr><td>74105\t<\/td><td>\tJ-K master-slave flip-flop<\/td><\/tr>\n<tr><td>74106\t<\/td><td>\tdual J-K negative-edge-triggered flip-flop with preset and clear<\/td><\/tr>\n<tr><td>74107\t<\/td><td>\tdual J-K flip-flop with clear<\/td><\/tr>\n<tr><td>74108\t<\/td><td>\tdual J-K negative-edge-triggered flip-flop with preset, common clear, and common clock<\/td><\/tr>\n<tr><td>74109\t<\/td><td>\tdual J-Not-K positive-edge-triggered flip-flop with clear and preset<\/td><\/tr>\n<tr><td>74110\t<\/td><td>\tAND-gated J-K master-slave flip-flop with data lockout<\/td><\/tr>\n<tr><td>74111\t<\/td><td>\tdual J-K master-slave flip-flop with data lockout<\/td><\/tr>\n<tr><td>74112\t<\/td><td>\tdual J-K negative-edge-triggered flip-flop with clear and preset<\/td><\/tr>\n<tr><td>74113\t<\/td><td>\tdual J-K negative-edge-triggered flip-flop with preset<\/td><\/tr>\n<tr><td>74114\t<\/td><td>\tdual J-K negative-edge-triggered flip-flop with preset, common clock and clear<\/td><\/tr>\n<tr><td>74116\t<\/td><td>\tdual 4-bit latch with clear<\/td><\/tr>\n<tr><td>74118\t<\/td><td>\thex set\/reset latch<\/td><\/tr>\n<tr><td>74119\t<\/td><td>\thex set\/reset latch<\/td><\/tr>\n<tr><td>74120\t<\/td><td>\tdual pulse synchronizer\/drivers<\/td><\/tr>\n<tr><td>74121\t<\/td><td>\tmonostable\u00a0multivibrator<\/td><\/tr>\n<tr><td>74122\t<\/td><td>\tretriggerable monostable multivibrator with clear<\/td><\/tr>\n<tr><td>74123\t<\/td><td>\tdual retriggerable monostable multivibrator with clear<\/td><\/tr>\n<tr><td>74124\t<\/td><td>\tdual\u00a0voltage-controlled oscillator<\/td><\/tr>\n<tr><td>74125\t<\/td><td>\tquad bus buffer with\u00a0three-state\u00a0outputs, negative enable<\/td><\/tr>\n<tr><td>74126\t<\/td><td>\tquad bus buffer with three-state outputs, positive enable<\/td><\/tr>\n<tr><td>74128\t<\/td><td>\tquad 2-input NOR Line driver<\/td><\/tr>\n<tr><td>74130\t<\/td><td>\tquad 2-input AND gate buffer with 30\u00a0V open collector outputs<\/td><\/tr>\n<tr><td>74131\t<\/td><td>\tquad 2-input AND gate buffer with 15\u00a0V open collector outputs<\/td><\/tr>\n<tr><td>74132\t<\/td><td>\tquad 2-input NAND schmitt trigger<\/td><\/tr>\n<tr><td>74133\t<\/td><td>\t13-input NAND gate<\/td><\/tr>\n<tr><td>74134\t<\/td><td>\t12-input NAND gate with three-state output<\/td><\/tr>\n<tr><td>74135\t<\/td><td>\tquad exclusive-or\/NOR gate<\/td><\/tr>\n<tr><td>74136\t<\/td><td>\tquad 2-input\u00a0XOR gate\u00a0with open collector outputs<\/td><\/tr>\n<tr><td>74137\t<\/td><td>\t3 to 8-line decoder\/demultiplexer\u00a0with address latch<\/td><\/tr>\n<tr><td>74138\t<\/td><td>\t3 to 8-line decoder\/demultiplexer<\/td><\/tr>\n<tr><td>74139\t<\/td><td>\tdual 2 to 4-line decoder\/demultiplexer<\/td><\/tr>\n<tr><td>74140\t<\/td><td>\tdual 4-input NAND line driver<\/td><\/tr>\n<tr><td>74141\t<\/td><td>\tBCD to decimal decoder\/driver for\u00a0cold-cathode\u00a0indicator\/Nixie tube<\/td><\/tr>\n<tr><td>74142\t<\/td><td>\tdecade counter\/latch\/decoder\/driver for Nixie tubes<\/td><\/tr>\n<tr><td>74143\t<\/td><td>\tdecade counter\/latch\/decoder\/7-segment driver, 15\u00a0ma constant current<\/td><\/tr>\n<tr><td>74144\t<\/td><td>\tdecade counter\/latch\/decoder\/7-segment driver, 15\u00a0V open collector outputs<\/td><\/tr>\n<tr><td>74145\t<\/td><td>\tBCD to decimal decoder\/driver<\/td><\/tr>\n<tr><td>74147\t<\/td><td>\t10-line to 4-line priority encoder<\/td><\/tr>\n<tr><td>74148\t<\/td><td>\t8-line to 3-line priority encoder<\/td><\/tr>\n<tr><td>74150\t<\/td><td>\t16-line to 1-line data selector\/multiplexer<\/td><\/tr>\n<tr><td>74151\t<\/td><td>\t8-line to 1-line data selector\/multiplexer<\/td><\/tr>\n<tr><td>74152\t<\/td><td>\t8-line to 1-line data selector\/multiplexer<\/td><\/tr>\n<tr><td>74153\t<\/td><td>\tdual 4-line to 1-line data selector\/multiplexer<\/td><\/tr>\n<tr><td>74154\t<\/td><td>\t4-line to 16-line decoder\/demultiplexer<\/td><\/tr>\n<tr><td>74155\t<\/td><td>\tdual 2-line to 4-line decoder\/demultiplexer<\/td><\/tr>\n<tr><td>74156\t<\/td><td>\tdual 2-line to 4-line decoder\/demultiplexer with open collector outputs<\/td><\/tr>\n<tr><td>74157\t<\/td><td>\tquad 2-line to 1-line data selector\/multiplexer, noninverting<\/td><\/tr>\n<tr><td>74158\t<\/td><td>\tquad 2-line to 1-line data selector\/multiplexer, inverting<\/td><\/tr>\n<tr><td>74159\t<\/td><td>\t4-line to 16-line decoder\/demultiplexer with open collector outputs<\/td><\/tr>\n<tr><td>74160\t<\/td><td>\tsynchronous 4-bit decade counter with asynchronous clear<\/td><\/tr>\n<tr><td>74161\t<\/td><td>\tsynchronous 4-bit binary counter with asynchronous clear<\/td><\/tr>\n<tr><td>74162\t<\/td><td>\tsynchronous 4-bit decade counter with synchronous clear<\/td><\/tr>\n<tr><td>74163\t<\/td><td>\tsynchronous 4-bit binary counter with synchronous clear<\/td><\/tr>\n<tr><td>74164\t<\/td><td>\t8-bit parallel-out serial shift register with asynchronous clear<\/td><\/tr>\n<tr><td>74165\t<\/td><td>\t8-bit serial shift register, parallel Load, complementary outputs<\/td><\/tr>\n<tr><td>74166\t<\/td><td>\tparallel-Load 8-bit shift register<\/td><\/tr>\n<tr><td>74167\t<\/td><td>\tsynchronous decade rate multiplier<\/td><\/tr>\n<tr><td>74168\t<\/td><td>\tsynchronous 4-bit up\/down decade counter<\/td><\/tr>\n<tr><td>74169\t<\/td><td>\tsynchronous 4-bit up\/down binary counter<\/td><\/tr>\n<tr><td>74170\t<\/td><td>\t4 by 4 register file with open collector outputs<\/td><\/tr>\n<tr><td>74171\t<\/td><td>\tquad D-type flip-flops with clear<\/td><\/tr>\n<tr><td>74172\t<\/td><td>\t16-bit multiple port register file with three-state outputs<\/td><\/tr>\n<tr><td>74173\t<\/td><td>\tquad d flip-flop with three-state outputs<\/td><\/tr>\n<tr><td>74174\t<\/td><td>\thex d flip-flop with common clear<\/td><\/tr>\n<tr><td>74175\t<\/td><td>\tquad d edge-triggered flip-flop with complementary outputs and asynchronous clear<\/td><\/tr>\n<tr><td>74176\t<\/td><td>\tpresettable decade (bi-quinary) counter\/latch<\/td><\/tr>\n<tr><td>74177\t<\/td><td>\tpresettable binary counter\/latch<\/td><\/tr>\n<tr><td>74178\t<\/td><td>\t4-bit parallel-access shift register<\/td><\/tr>\n<tr><td>74179\t<\/td><td>\t4-bit parallel-access shift register with asynchronous clear and complementary Qd\u00a0outputs<\/td><\/tr>\n<tr><td>74180\t<\/td><td>\t9-bit odd\/even\u00a0parity bit\u00a0generator and checker<\/td><\/tr>\n<tr><td>74181\t<\/td><td>\t4-bit arithmetic logic unit and function generator<\/td><\/tr>\n<tr><td>74182\t<\/td><td>\tlookahead carry generator<\/td><\/tr>\n<tr><td>74183\t<\/td><td>\tdual carry-save\u00a0full adder<\/td><\/tr>\n<tr><td>74184\t<\/td><td>\tBCD to binary converter<\/td><\/tr>\n<tr><td>74185\t<\/td><td>\t6-bit binary to BCD converter<\/td><\/tr>\n<tr><td>74186\t<\/td><td>\t512-bit (64&#215;8)\u00a0read-only memory\u00a0with open collector outputs<\/td><\/tr>\n<tr><td>74187\t<\/td><td>\t1024-bit (256&#215;4) read only memory with open collector outputs<\/td><\/tr>\n<tr><td>74188\t<\/td><td>\t256-bit (32&#215;8)\u00a0programmable read-only memory\u00a0with open collector outputs<\/td><\/tr>\n<tr><td>74189\t<\/td><td>\t64-bit (16&#215;4) RAM with inverting three-state outputs<\/td><\/tr>\n<tr><td>74190\t<\/td><td>\tsynchronous up\/down decade counter<\/td><\/tr>\n<tr><td>74191\t<\/td><td>\tsynchronous up\/down binary counter<\/td><\/tr>\n<tr><td>74192\t<\/td><td>\tsynchronous up\/down decade counter with clear<\/td><\/tr>\n<tr><td>74193\t<\/td><td>\tsynchronous up\/down 4-bit binary counter with clear<\/td><\/tr>\n<tr><td>74194\t<\/td><td>\t4-bit bidirectional universal shift register<\/td><\/tr>\n<tr><td>74195\t<\/td><td>\t4-bit parallel-access shift register<\/td><\/tr>\n<tr><td>74196\t<\/td><td>\tpresettable decade counter\/latch<\/td><\/tr>\n<tr><td>74197\t<\/td><td>\tpresettable binary counter\/latch<\/td><\/tr>\n<tr><td>74198\t<\/td><td>\t8-bit bidirectional universal shift register<\/td><\/tr>\n<tr><td>74199\t<\/td><td>\t8-bit bidirectional universal shift register with J-Not-K serial inputs<\/td><\/tr>\n<tr><td>74200\t<\/td><td>\t256-bit ram with three-state outputs<\/td><\/tr>\n<tr><td>74201\t<\/td><td>\t256-bit (256&#215;1) ram with three-state outputs<\/td><\/tr>\n<tr><td>74206\t<\/td><td>\t256-bit ram with open collector outputs<\/td><\/tr>\n<tr><td>74209\t<\/td><td>\t1024-bit (1024&#215;1) ram with three-state output<\/td><\/tr>\n<tr><td>74210\t<\/td><td>\toctal buffer<\/td><\/tr>\n<tr><td>74219\t<\/td><td>\t64-bit (16&#215;4) RAM with noninverting three-state outputs<\/td><\/tr>\n<tr><td>74221\t<\/td><td>\tdual monostable multivibrator with schmitt trigger input<\/td><\/tr>\n<tr><td>74222\t<\/td><td>\t16 by 4 synchronous\u00a0FIFO\u00a0memory with three-state outputs<\/td><\/tr>\n<tr><td>74224\t<\/td><td>\t16 by 4 synchronous FIFO memory with three-state outputs<\/td><\/tr>\n<tr><td>74225\t<\/td><td>\tasynchronous 16&#215;5 FIFO memory<\/td><\/tr>\n<tr><td>74226\t<\/td><td>\t4-bit parallel latched bus transceiver with three-state outputs<\/td><\/tr>\n<tr><td>74227\t<\/td><td>\t64-bit fifo memories 16&#215;4<\/td><\/tr>\n<tr><td>74228\t<\/td><td>\t64-bit fifo memories 16&#215;4 open-collector outputs<\/td><\/tr>\n<tr><td>74230\t<\/td><td>\toctal buffer\/driver with three-state outputs, true and complementary inputs<\/td><\/tr>\n<tr><td>74231\t<\/td><td>\toctal buffer and line driver with three-state outputs, G and \/G complementary inputs<\/td><\/tr>\n<tr><td>74232\t<\/td><td>\tquad NOR Schmitt trigger<\/td><\/tr>\n<tr><td>74237\t<\/td><td>\t3-of-8 decoder\/demultiplexer with address latch, active high outputs<\/td><\/tr>\n<tr><td>74238\t<\/td><td>\t3-of-8 decoder\/demultiplexer, active high outputs<\/td><\/tr>\n<tr><td>74239\t<\/td><td>\tdual 2-of-4 decoder\/demultiplexer, active high outputs<\/td><\/tr>\n<tr><td>74240\t<\/td><td>\toctal buffer with Inverted three-state outputs<\/td><\/tr>\n<tr><td>74241\t<\/td><td>\toctal buffer with noninverted three-state outputs<\/td><\/tr>\n<tr><td>74242\t<\/td><td>\tquad bus transceiver with Inverted three-state outputs<\/td><\/tr>\n<tr><td>74243\t<\/td><td>\tquad bus transceiver with noninverted three-state outputs<\/td><\/tr>\n<tr><td>74244\t<\/td><td>\toctal buffer with noninverted three-state outputs<\/td><\/tr>\n<tr><td>74245\t<\/td><td>\toctal bus transceiver with noninverted three-state outputs<\/td><\/tr>\n<tr><td>74246\t<\/td><td>\tBCD to 7-segment decoder\/driver with 30\u00a0V open collector outputs<\/td><\/tr>\n<tr><td>74247\t<\/td><td>\tBCD to 7-segment decoder\/driver with 15\u00a0V open collector outputs<\/td><\/tr>\n<tr><td>74248\t<\/td><td>\tBCD to 7-segment decoder\/driver with Internal Pull-up outputs<\/td><\/tr>\n<tr><td>74249\t<\/td><td>\tBCD to 7-segment decoder\/driver with open collector outputs<\/td><\/tr>\n<tr><td>74250\t<\/td><td>\t1 of 16 data selectors\/multiplexers<\/td><\/tr>\n<tr><td>74251\t<\/td><td>\t8-line to 1-line data selector\/multiplexer with complementary three-state outputs<\/td><\/tr>\n<tr><td>74253\t<\/td><td>\tdual 4-line to 1-line data selector\/multiplexer with three-state outputs<\/td><\/tr>\n<tr><td>74255\t<\/td><td>\tdual 4-bit addressable latch<\/td><\/tr>\n<tr><td>74256\t<\/td><td>\tdual 4-bit addressable latch<\/td><\/tr>\n<tr><td>74257\t<\/td><td>\tquad 2-line to 1-line data selector\/multiplexer with noninverted three-state outputs<\/td><\/tr>\n<tr><td>74258\t<\/td><td>\tquad 2-line to 1-line data selector\/multiplexer with Inverted three-state outputs<\/td><\/tr>\n<tr><td>74259\t<\/td><td>\t8-bit addressable latch<\/td><\/tr>\n<tr><td>74260\t<\/td><td>\tdual 5-input NOR gate<\/td><\/tr>\n<tr><td>74261\t<\/td><td>\t2-bit by 4-bit parallel binary multiplier<\/td><\/tr>\n<tr><td>74264\t<\/td><td>\tlook ahead carry generator<\/td><\/tr>\n<tr><td>74265\t<\/td><td>\tquad complementary output elements<\/td><\/tr>\n<tr><td>74266\t<\/td><td>\tquad 2-input XNOR gate with\u00a0open collector\u00a0outputs<\/td><\/tr>\n<tr><td>74268\t<\/td><td>\thex d-type latches three-state outputs, common output control, common enable<\/td><\/tr>\n<tr><td>74270\t<\/td><td>\t2048-bit (512&#215;4) read only memory with open collector outputs<\/td><\/tr>\n<tr><td>74271\t<\/td><td>\t2048-bit (256&#215;8) read only memory with open collector outputs<\/td><\/tr>\n<tr><td>74273\t<\/td><td>\t8-bit register with reset<\/td><\/tr>\n<tr><td>74274\t<\/td><td>\t4-bit by 4-bit binary multiplier<\/td><\/tr>\n<tr><td>74275\t<\/td><td>\t7-bit slice\u00a0Wallace tree<\/td><\/tr>\n<tr><td>74276\t<\/td><td>\tquad J-Not-K edge-triggered\u00a0Flip-Flops\u00a0with separate clocks, common preset and clear<\/td><\/tr>\n<tr><td>74278\t<\/td><td>\t4-bit cascadeable priority registers with latched data inputs<\/td><\/tr>\n<tr><td>74279\t<\/td><td>\tquad set-reset latch<\/td><\/tr>\n<tr><td>74280\t<\/td><td>\t9-bit odd\/even\u00a0Parity bit\u00a0Generator\/checker<\/td><\/tr>\n<tr><td>74281\t<\/td><td>\t4-bit parallel binary accumulator<\/td><\/tr>\n<tr><td>74282\t<\/td><td>\tlook-ahead carry generator with selectable carry inputs<\/td><\/tr>\n<tr><td>74283\t<\/td><td>\t4-bit binary\u00a0Full adder<\/td><\/tr>\n<tr><td>74284\t<\/td><td>\t4-bit by 4-bit parallel binary multiplier (low order 4 bits of product)<\/td><\/tr>\n<tr><td>74285\t<\/td><td>\t4-bit by 4-bit parallel binary multiplier (high order 4 bits of product)<\/td><\/tr>\n<tr><td>74286\t<\/td><td>\t9-bit parity generator\/checker with bus driver parity I\/O port<\/td><\/tr>\n<tr><td>74287\t<\/td><td>\t1024-bit (256&#215;4)\u00a0programmable read-only memory\u00a0with three-state outputs<\/td><\/tr>\n<tr><td>74288\t<\/td><td>\t256-bit (32&#215;8) programmable read-only memory with three-state outputs<\/td><\/tr>\n<tr><td>74289\t<\/td><td>\t64-bit (16&#215;4) RAM with open collector outputs<\/td><\/tr>\n<tr><td>74290\t<\/td><td>\tdecade counter (separate divide-by-2 and divide-by-5 sections)<\/td><\/tr>\n<tr><td>74291\t<\/td><td>\t4-bit universal shift register, binary up\/down counter, synchronous<\/td><\/tr>\n<tr><td>74292\t<\/td><td>\tprogrammable frequency divider\/digital timer<\/td><\/tr>\n<tr><td>74293\t<\/td><td>\t4-bit binary counter (separate divide-by-2 and divide-by-8 sections)<\/td><\/tr>\n<tr><td>74294\t<\/td><td>\tprogrammable frequency divider\/digital timer<\/td><\/tr>\n<tr><td>74295\t<\/td><td>\t4-bit bidirectional register with three-state outputs<\/td><\/tr>\n<tr><td>74297\t<\/td><td>\tdigital phase-locked-loop filter<\/td><\/tr>\n<tr><td>74298\t<\/td><td>\tquad 2-input multiplexer with storage<\/td><\/tr>\n<tr><td>74299\t<\/td><td>\t8-bit bidirectional universal shift\/storage register with three-state outputs<\/td><\/tr>\n<tr><td>74301\t<\/td><td>\t256-bit (256&#215;1)\u00a0random access memory\u00a0with open collector output<\/td><\/tr>\n<tr><td>74309\t<\/td><td>\t1024-bit (1024&#215;1) random access memory with open collector output<\/td><\/tr>\n<tr><td>74310\t<\/td><td>\toctal buffer with Schmitt trigger inputs<\/td><\/tr>\n<tr><td>74314\t<\/td><td>\t1024-bit random access memory<\/td><\/tr>\n<tr><td>74319\t<\/td><td>\t64-bit random access memories 16&#215;4 open collector outputs<\/td><\/tr>\n<tr><td>74320\t<\/td><td>\tcrystal controlled\u00a0oscillator<\/td><\/tr>\n<tr><td>74321\t<\/td><td>\tcrystal-controlled oscillators with F\/2 and F\/4 count-down outputs<\/td><\/tr>\n<tr><td>74322\t<\/td><td>\t8-bit shift register with sign extend, three-state outputs<\/td><\/tr>\n<tr><td>74323\t<\/td><td>\t8-bit bidirectional universal shift\/storage register with three-state outputs<\/td><\/tr>\n<tr><td>74324\t<\/td><td>\tvoltage controlled oscillator (or crystal controlled)<\/td><\/tr>\n<tr><td>74340\t<\/td><td>\toctal buffer with Schmitt trigger inputs and three-state inverted outputs<\/td><\/tr>\n<tr><td>74341\t<\/td><td>\toctal buffer with Schmitt trigger inputs and three-state noninverted outputs<\/td><\/tr>\n<tr><td>74344\t<\/td><td>\toctal buffer with Schmitt trigger inputs and three-state noninverted outputs<\/td><\/tr>\n<tr><td>74347\t<\/td><td>\tbcd to seven segment decoders\/drivers open collector outputs, low voltage version of 7447<\/td><\/tr>\n<tr><td>74348\t<\/td><td>\t8 to 3-line priority encoder with three-state outputs<\/td><\/tr>\n<tr><td>74350\t<\/td><td>\t4-bit shifter with three-state outputs<\/td><\/tr>\n<tr><td>74351\t<\/td><td>\tdual 8-line to 1-line data selectors\/multiplexers with three-state outputs and 4 common data inputs<\/td><\/tr>\n<tr><td>74352\t<\/td><td>\tdual 4-line to 1-line data selectors\/multiplexers with inverting outputs<\/td><\/tr>\n<tr><td>74353\t<\/td><td>\tdual 4-line to 1-line data selectors\/multiplexers with inverting three-state outputs<\/td><\/tr>\n<tr><td>74354\t<\/td><td>\t8 to 1-line data selector\/multiplexer with transparent latch, three-state outputs<\/td><\/tr>\n<tr><td>74355\t<\/td><td>\t8-line to 1-line data selector\/multiplexer with transparent registers, open-collector outputs<\/td><\/tr>\n<tr><td>74356\t<\/td><td>\t8 to 1-line data selector\/multiplexer with edge-triggered register, three-state outputs<\/td><\/tr>\n<tr><td>74357\t<\/td><td>\t8-line to 1-line data selectors\/multiplexers\/edge-triggered registers, open-collector outputs<\/td><\/tr>\n<tr><td>74361\t<\/td><td>\tbubble memory\u00a0function timing generator<\/td><\/tr>\n<tr><td>74362\t<\/td><td>\tfour-phase clock\u00a0generator\/driver<\/td><\/tr>\n<tr><td>74363\t<\/td><td>\toctal three-state D-latches<\/td><\/tr>\n<tr><td>74365\t<\/td><td>\thex buffer with noninverted three-state outputs<\/td><\/tr>\n<tr><td>74366\t<\/td><td>\thex buffer with Inverted three-state outputs<\/td><\/tr>\n<tr><td>74367\t<\/td><td>\thex buffer with noninverted three-state outputs<\/td><\/tr>\n<tr><td>74368\t<\/td><td>\thex buffer with Inverted three-state outputs<\/td><\/tr>\n<tr><td>74370\t<\/td><td>\t2048-bit (512&#215;4) read-only memory with three-state outputs<\/td><\/tr>\n<tr><td>74371\t<\/td><td>\t2048-bit (256&#215;8) read-only memory with three-state outputs<\/td><\/tr>\n<tr><td>74373\t<\/td><td>\toctal transparent latch with three-state outputs<\/td><\/tr>\n<tr><td>74374\t<\/td><td>\toctal register with three-state outputs<\/td><\/tr>\n<tr><td>74375\t<\/td><td>\tquad bistable latch<\/td><\/tr>\n<tr><td>74376\t<\/td><td>\tquad J-Not-K flip-flop with common clock and common clear<\/td><\/tr>\n<tr><td>74377\t<\/td><td>\t8-bit register with clock enable<\/td><\/tr>\n<tr><td>74378\t<\/td><td>\t6-bit register with clock enable<\/td><\/tr>\n<tr><td>74379\t<\/td><td>\t4-bit register with clock enable and complementary outputs<\/td><\/tr>\n<tr><td>74380\t<\/td><td>\t8-bit multifunction register<\/td><\/tr>\n<tr><td>74381\t<\/td><td>\t4-bit arithmetic logic unit\/function generator with generate and propagate outputs<\/td><\/tr>\n<tr><td>74382\t<\/td><td>\t4-bit arithmetic logic unit\/function generator with ripple carry and overflow outputs<\/td><\/tr>\n<tr><td>74384\t<\/td><td>\t8-bit by 1-bit two&#8217;s complement multipliers<\/td><\/tr>\n<tr><td>74385\t<\/td><td>\tquad 4-bit adder\/subtractor<\/td><\/tr>\n<tr><td>74386\t<\/td><td>\tquad 2-input\u00a0XOR gate<\/td><\/tr>\n<tr><td>74387\t<\/td><td>\t1024-bit (256&#215;4) programmable read-only memory with open collector outputs<\/td><\/tr>\n<tr><td>74388\t<\/td><td>\t4-bit register with standard and three-state outputs<\/td><\/tr>\n<tr><td>74390\t<\/td><td>\tdual 4-bit decade counter<\/td><\/tr>\n<tr><td>74393\t<\/td><td>\tdual 4-bit binary counter<\/td><\/tr>\n<tr><td>74395\t<\/td><td>\t4-bit universal shift register with three-state outputs<\/td><\/tr>\n<tr><td>74396\t<\/td><td>\toctal storage registers, parallel access<\/td><\/tr>\n<tr><td>74398\t<\/td><td>\tquad 2-input multiplexers with storage and complementary outputs<\/td><\/tr>\n<tr><td>74399\t<\/td><td>\tquad 2-input multiplexer with storage<\/td><\/tr>\n<tr><td>74405\t<\/td><td>\t1 to 8 decoder, equivalent to Intel 8205, only found as UCY74S405 so might be non-TI number<\/td><\/tr>\n<tr><td>74408\t<\/td><td>\t8-bit\u00a0parity\u00a0tree<\/td><\/tr>\n<tr><td>74412\t<\/td><td>\tmulti-mode buffered 8-bit latches with three-state outputs and clear<\/td><\/tr>\n<tr><td>74422\t<\/td><td>\tre-triggerable mono-stable multivibrators, two inputs<\/td><\/tr>\n<tr><td>74423\t<\/td><td>\tdual retriggerable monostable multivibrator<\/td><\/tr>\n<tr><td>74424\t<\/td><td>\ttwo-phase clock\u00a0generator\/driver<\/td><\/tr>\n<tr><td>74425\t<\/td><td>\tquad gates with three-state outputs and active low enables<\/td><\/tr>\n<tr><td>74426\t<\/td><td>\tquad gates with three-state outputs and active high enables<\/td><\/tr>\n<tr><td>74428\t<\/td><td>\tsystem controller for 8080a<\/td><\/tr>\n<tr><td>74436\t<\/td><td>\tline driver\/memory driver circuits &#8211; mos memory interface, damping output resistor<\/td><\/tr>\n<tr><td>74437\t<\/td><td>\tline driver\/memory driver circuits &#8211; mos memory interface<\/td><\/tr>\n<tr><td>74438\t<\/td><td>\tsystem controller for 8080a<\/td><\/tr>\n<tr><td>74440\t<\/td><td>\tquad tridirectional bus transceiver with noninverted open collector outputs<\/td><\/tr>\n<tr><td>74441\t<\/td><td>\tquad tridirectional bus transceiver with Inverted open collector outputs<\/td><\/tr>\n<tr><td>74442\t<\/td><td>\tquad tridirectional bus transceiver with noninverted three-state outputs<\/td><\/tr>\n<tr><td>74443\t<\/td><td>\tquad tridirectional bus transceiver with Inverted three-state outputs<\/td><\/tr>\n<tr><td>74444\t<\/td><td>\tquad tridirectional bus transceiver with Inverted and noninverted three-state outputs<\/td><\/tr>\n<tr><td>74445\t<\/td><td>\tbcd-to-decimal decoders\/drivers<\/td><\/tr>\n<tr><td>74446\t<\/td><td>\tquad bus transceivers with direction controls<\/td><\/tr>\n<tr><td>74447\t<\/td><td>\tbcd-to-seven-segment decoders\/drivers, low voltage version of 74247<\/td><\/tr>\n<tr><td>74448\t<\/td><td>\tquad tridirectional bus transceiver with Inverted and noninverted open collector outputs<\/td><\/tr>\n<tr><td>74449\t<\/td><td>\tquad bus transceivers with direction controls, true outputs<\/td><\/tr>\n<tr><td>74450\t<\/td><td>\t16-to-1 multiplexer with complementary outputs<\/td><\/tr>\n<tr><td>74451\t<\/td><td>\tdual 8-to-1 multiplexer<\/td><\/tr>\n<tr><td>74452\t<\/td><td>\tdual decade counter, synchronous<\/td><\/tr>\n<tr><td>74453\t<\/td><td>\tdual binary counter, synchronous<\/td><\/tr>\n<tr><td>74453\t<\/td><td>\tquad 4-to-1 multiplexer<\/td><\/tr>\n<tr><td>74454\t<\/td><td>\tdual decade up\/down counter, synchronous, preset input<\/td><\/tr>\n<tr><td>74455\t<\/td><td>\tdual binary up\/down counter, synchronous, preset input<\/td><\/tr>\n<tr><td>74456\t<\/td><td>\tNBCD (Natural binary coded decimal) adder<\/td><\/tr>\n<tr><td>74460\t<\/td><td>\tbus transfer switch<\/td><\/tr>\n<tr><td>74461\t<\/td><td>\t8-bit presettable binary counter with three-state outputs<\/td><\/tr>\n<tr><td>74462\t<\/td><td>\tfiber-optic link transmitter<\/td><\/tr>\n<tr><td>74463\t<\/td><td>\tfiber-optic link receiver<\/td><\/tr>\n<tr><td>74465\t<\/td><td>\toctal buffer with three-state true outputs<\/td><\/tr>\n<tr><td>74466\t<\/td><td>\toctal buffers with three-state inverted outputs<\/td><\/tr>\n<tr><td>74467\t<\/td><td>\toctal buffers with three-state true outputs<\/td><\/tr>\n<tr><td>74468\t<\/td><td>\toctal buffers with three-state inverted outputs<\/td><\/tr>\n<tr><td>74470\t<\/td><td>\t2048-bit (256&#215;8) programmable read-only memory with open collector outputs<\/td><\/tr>\n<tr><td>74471\t<\/td><td>\t2048-bit (256&#215;8) programmable read-only memory with three-state outputs<\/td><\/tr>\n<tr><td>74472\t<\/td><td>\tprogrammable read-only memory with open collector outputs<\/td><\/tr>\n<tr><td>74473\t<\/td><td>\tprogrammable read-only memory with three-state outputs<\/td><\/tr>\n<tr><td>74474\t<\/td><td>\tprogrammable read-only memory with open collector outputs<\/td><\/tr>\n<tr><td>74475\t<\/td><td>\tprogrammable read-only memory with three-state outputs<\/td><\/tr>\n<tr><td>74481\t<\/td><td>\t4-bit slice cascadable processor elements<\/td><\/tr>\n<tr><td>74482\t<\/td><td>\t4-bit slice expandable control elements<\/td><\/tr>\n<tr><td>74484\t<\/td><td>\tBCD-to-binary converter<\/td><\/tr>\n<tr><td>74485\t<\/td><td>\tbinary-to-BCD converter<\/td><\/tr>\n<tr><td>74490\t<\/td><td>\tdual decade counter<\/td><\/tr>\n<tr><td>74491\t<\/td><td>\t10-bit binary up\/down counter with limited preset and three-state outputs<\/td><\/tr>\n<tr><td>74498\t<\/td><td>\t8-bit bidirectional shift register with parallel inputs and three-state outputs<\/td><\/tr>\n<tr><td>74508\t<\/td><td>\t8-bit multiplier\/divider<\/td><\/tr>\n<tr><td>74518\t<\/td><td>\t8-bit comparator with open collector output, input pull-up resistor<\/td><\/tr>\n<tr><td>74519\t<\/td><td>\t8-bit comparator with open collector output<\/td><\/tr>\n<tr><td>74520\t<\/td><td>\t8-bit comparator with inverted totem-pole output, input pull-up resistor<\/td><\/tr>\n<tr><td>74521\t<\/td><td>\t8-bit comparator with inverted totem-pole output<\/td><\/tr>\n<tr><td>74522\t<\/td><td>\t8-bit comparator with inverted open-collector output, input pull-up resistor<\/td><\/tr>\n<tr><td>74526\t<\/td><td>\tfuse programmable identity comparator, 16 bit<\/td><\/tr>\n<tr><td>74527\t<\/td><td>\tfuse programmable identity comparator, 8 bit + 4 bit conventional Identity comparator<\/td><\/tr>\n<tr><td>74528\t<\/td><td>\tfuse programmable Identity comparator, 12 bit<\/td><\/tr>\n<tr><td>74531\t<\/td><td>\toctal transparent latch with 32 ma three-state outputs<\/td><\/tr>\n<tr><td>74532\t<\/td><td>\toctal register with 32 ma three-state outputs<\/td><\/tr>\n<tr><td>74533\t<\/td><td>\toctal transparent latch with inverting three-state outputs<\/td><\/tr>\n<tr><td>74534\t<\/td><td>\toctal register with inverting three-state outputs<\/td><\/tr>\n<tr><td>74535\t<\/td><td>\toctal transparent latch with inverting three-state outputs<\/td><\/tr>\n<tr><td>74536\t<\/td><td>\toctal register with inverting 32 ma three-state outputs<\/td><\/tr>\n<tr><td>74537\t<\/td><td>\tBCD to decimal decoder with three-state outputs<\/td><\/tr>\n<tr><td>74538\t<\/td><td>\t1 of 8 decoder with three-state outputs<\/td><\/tr>\n<tr><td>74539\t<\/td><td>\tdual 1 of 4 decoder with three-state outputs<\/td><\/tr>\n<tr><td>74540\t<\/td><td>\tinverting octal buffer with three-state outputs<\/td><\/tr>\n<tr><td>74541\t<\/td><td>\tnon-inverting octal buffer with three-state outputs<\/td><\/tr>\n<tr><td>74544\t<\/td><td>\tnon-inverting octal registered transceiver with three-state outputs<\/td><\/tr>\n<tr><td>74558\t<\/td><td>\t8-bit by 8-bit multiplier with three-state outputs<\/td><\/tr>\n<tr><td>74560\t<\/td><td>\t4-bit decade counter with three-state outputs<\/td><\/tr>\n<tr><td>74561\t<\/td><td>\t4-bit binary counter with three-state outputs<\/td><\/tr>\n<tr><td>74563\t<\/td><td>\t8-bit d-type transparent latch with inverting three-state outputs<\/td><\/tr>\n<tr><td>74564\t<\/td><td>\t8-bit d-type edge-triggered register with inverting three-state outputs<\/td><\/tr>\n<tr><td>74568\t<\/td><td>\tdecade up\/down counter with three-state outputs<\/td><\/tr>\n<tr><td>74569\t<\/td><td>\tbinary up\/down counter with three-state outputs<\/td><\/tr>\n<tr><td>74573\t<\/td><td>\toctal D-type transparent latch with three-state outputs<\/td><\/tr>\n<tr><td>74574\t<\/td><td>\toctal D-type edge-triggered flip-flop with three-state outputs<\/td><\/tr>\n<tr><td>74575\t<\/td><td>\toctal D-type flip-flop with synchronous clear, three-state outputs<\/td><\/tr>\n<tr><td>74576\t<\/td><td>\toctal D-type flip-flop with inverting three-state outputs<\/td><\/tr>\n<tr><td>74577\t<\/td><td>\toctal D-type flip-flop with synchronous clear, inverting three-state outputs<\/td><\/tr>\n<tr><td>74580\t<\/td><td>\toctal transceiver\/latch with inverting three-state outputs<\/td><\/tr>\n<tr><td>74589\t<\/td><td>\t8-bit shift register with input latch, three-state outputs<\/td><\/tr>\n<tr><td>74590\t<\/td><td>\t8-bit binary counter with output registers and three-state outputs<\/td><\/tr>\n<tr><td>74591\t<\/td><td>\t8-bit binary counters with output registers, open-collector outputs<\/td><\/tr>\n<tr><td>74592\t<\/td><td>\t8-bit binary counter with input registers<\/td><\/tr>\n<tr><td>74593\t<\/td><td>\t8-bit binary counter with input registers and three-state outputs<\/td><\/tr>\n<tr><td>74594\t<\/td><td>\t8-bit shift registers with output latches<\/td><\/tr>\n<tr><td>74595\t<\/td><td>\t8-bit shift registers with output latches, three-state parallel outputs<\/td><\/tr>\n<tr><td>74596\t<\/td><td>\t8-bit shift registers with output latches, open-collector parallel outputs<\/td><\/tr>\n<tr><td>74597\t<\/td><td>\t8-bit shift registers with input latches<\/td><\/tr>\n<tr><td>74598\t<\/td><td>\t8-bit shift register with input latches<\/td><\/tr>\n<tr><td>74599\t<\/td><td>\t8-bit shift registers with output latches, open-collector outputs<\/td><\/tr>\n<tr><td>74600\t<\/td><td>\tdynamic memory refresh controller, transparent and burst modes, for 4K or 16K drams<\/td><\/tr>\n<tr><td>74601\t<\/td><td>\tdynamic memory refresh controller, transparent and burst modes, for 64K drams<\/td><\/tr>\n<tr><td>74602\t<\/td><td>\tdynamic memory refresh controller, cycle steal and burst modes, for 4K or 16K drams<\/td><\/tr>\n<tr><td>74603\t<\/td><td>\tdynamic memory refresh controller, cycle steal and burst modes, for 64K drams<\/td><\/tr>\n<tr><td>74604\t<\/td><td>\toctal 2-input multiplexer with latch, high-speed, with three-state outputs<\/td><\/tr>\n<tr><td>74605\t<\/td><td>\tlatch, high-speed, with open collector outputs<\/td><\/tr>\n<tr><td>74606\t<\/td><td>\toctal 2-input multiplexer with latch, glitch-free, with three-state outputs<\/td><\/tr>\n<tr><td>74607\t<\/td><td>\toctal 2-input multiplexer with latch, glitch-free, with open collector outputs<\/td><\/tr>\n<tr><td>74608\t<\/td><td>\tmemory cycle controller<\/td><\/tr>\n<tr><td>74610\t<\/td><td>\tmemory mapper, latched, three-state outputs<\/td><\/tr>\n<tr><td>74611\t<\/td><td>\tmemory mapper, latched, open collector outputs<\/td><\/tr>\n<tr><td>74612\t<\/td><td>\tmemory mapper, three-state outputs<\/td><\/tr>\n<tr><td>74613\t<\/td><td>\tmemory mapper, open collector outputs<\/td><\/tr>\n<tr><td>74618\t<\/td><td>\tSchmitt-trigger positive-nand gates with totem-pole outputs<\/td><\/tr>\n<tr><td>74619\t<\/td><td>\tSchmitt-trigger inverters with totem-pole outputs<\/td><\/tr>\n<tr><td>74620\t<\/td><td>\toctal bus transceiver, inverting, three-state outputs<\/td><\/tr>\n<tr><td>74621\t<\/td><td>\toctal bus transceiver, noninverting, open collector outputs<\/td><\/tr>\n<tr><td>74622\t<\/td><td>\toctal bus transceiver, inverting, open collector outputs<\/td><\/tr>\n<tr><td>74623\t<\/td><td>\toctal bus transceiver, noninverting, three-state outputs<\/td><\/tr>\n<tr><td>74624\t<\/td><td>\tvoltage-controlled oscillator with enable control, range control, two-phase outputs<\/td><\/tr>\n<tr><td>74625\t<\/td><td>\tdual voltage-controlled oscillator with two-phase outputs<\/td><\/tr>\n<tr><td>74626\t<\/td><td>\tdual voltage-controlled oscillator with enable control, two-phase outputs<\/td><\/tr>\n<tr><td>74627\t<\/td><td>\tdual voltage-controlled oscillator<\/td><\/tr>\n<tr><td>74628\t<\/td><td>\tvoltage-controlled oscillator with enable control, range control, external temperature compensation, and two-phase outputs<\/td><\/tr>\n<tr><td>74629\t<\/td><td>\tdual voltage-controlled oscillator with enable control, range control<\/td><\/tr>\n<tr><td>74630\t<\/td><td>\t16-bit error detection and correction (EDAC) with three-state outputs<\/td><\/tr>\n<tr><td>74631\t<\/td><td>\t16-bit error detection and correction with open collector outputs<\/td><\/tr>\n<tr><td>74632\t<\/td><td>\t32-bit parallel error detection and correction, three-state outputs, byte-write<\/td><\/tr>\n<tr><td>74633\t<\/td><td>\t32-bit parallel error detection and correction, open-collector outputs, byte-write<\/td><\/tr>\n<tr><td>74634\t<\/td><td>\t32-bit parallel error detection and correction, three-state outputs<\/td><\/tr>\n<tr><td>74635\t<\/td><td>\t32-bit parallel error detection and correction, open-collector outputs<\/td><\/tr>\n<tr><td>74638\t<\/td><td>\toctal bus transceiver with inverting three-state outputs<\/td><\/tr>\n<tr><td>74639\t<\/td><td>\toctal bus transceiver with noninverting three-state outputs<\/td><\/tr>\n<tr><td>74640\t<\/td><td>\toctal bus transceiver with inverting three-state outputs<\/td><\/tr>\n<tr><td>74641\t<\/td><td>\toctal bus transceiver with noninverting open collector outputs<\/td><\/tr>\n<tr><td>74642\t<\/td><td>\toctal bus transceiver with inverting open collector outputs<\/td><\/tr>\n<tr><td>74643\t<\/td><td>\toctal bus transceiver with mix of inverting and noninverting three-state outputs<\/td><\/tr>\n<tr><td>74644\t<\/td><td>\toctal bus transceiver with mix of inverting and noninverting open collector outputs<\/td><\/tr>\n<tr><td>74645\t<\/td><td>\toctal bus transceiver<\/td><\/tr>\n<tr><td>74646\t<\/td><td>\toctal bus transceiver\/latch\/multiplexer with noninverting three-state outputs<\/td><\/tr>\n<tr><td>74647\t<\/td><td>\toctal bus transceiver\/latch\/multiplexer with noninverting open collector outputs<\/td><\/tr>\n<tr><td>74648\t<\/td><td>\toctal bus transceiver\/latch\/multiplexer with inverting three-state outputs<\/td><\/tr>\n<tr><td>74649\t<\/td><td>\toctal bus transceiver\/latch\/multiplexer with inverting open collector outputs<\/td><\/tr>\n<tr><td>74651\t<\/td><td>\toctal bus transceiver\/register with inverting three-state outputs<\/td><\/tr>\n<tr><td>74652\t<\/td><td>\toctal bus transceiver\/register with noninverting three-state outputs<\/td><\/tr>\n<tr><td>74653\t<\/td><td>\toctal bus transceiver\/register with inverting three-state and open collector outputs<\/td><\/tr>\n<tr><td>74654\t<\/td><td>\toctal bus transceiver\/register with noninverting three-state and open collector outputs<\/td><\/tr>\n<tr><td>74658\t<\/td><td>\toctal bus transceiver with Parity, inverting<\/td><\/tr>\n<tr><td>74659\t<\/td><td>\toctal bus transceiver with Parity, noninverting<\/td><\/tr>\n<tr><td>74664\t<\/td><td>\toctal bus transceiver with Parity, inverting<\/td><\/tr>\n<tr><td>74665\t<\/td><td>\toctal bus transceiver with Parity, noninverting<\/td><\/tr>\n<tr><td>74668\t<\/td><td>\tsynchronous 4-bit decade Up\/down counter<\/td><\/tr>\n<tr><td>74669\t<\/td><td>\tsynchronous 4-bit binary Up\/down counter<\/td><\/tr>\n<tr><td>74670\t<\/td><td>\t4 by 4 register File with three-state outputs<\/td><\/tr>\n<tr><td>74671\t<\/td><td>\t4-bit bidirectional shift register\/latch \/multiplexer with three-state outputs<\/td><\/tr>\n<tr><td>74672\t<\/td><td>\t4-bit bidirectional shift register\/latch\/multiplexer with three-state outputs<\/td><\/tr>\n<tr><td>74673\t<\/td><td>\t16-bit serial-in serial-out shift register with output storage registers, three-state outputs<\/td><\/tr>\n<tr><td>74674\t<\/td><td>\t16-bit parallel-in serial-out shift register with three-state outputs<\/td><\/tr>\n<tr><td>74677\t<\/td><td>\t16-bit address\u00a0comparator\u00a0with enable<\/td><\/tr>\n<tr><td>74678\t<\/td><td>\t16-bit address comparator with latch<\/td><\/tr>\n<tr><td>74679\t<\/td><td>\t12-bit address comparator with latch<\/td><\/tr>\n<tr><td>74680\t<\/td><td>\t12-bit address comparator with enable<\/td><\/tr>\n<tr><td>74681\t<\/td><td>\t4-bit parallel binary accumulator<\/td><\/tr>\n<tr><td>74682\t<\/td><td>\t8-bit\u00a0magnitude comparator<\/td><\/tr>\n<tr><td>74683\t<\/td><td>\t8-bit magnitude comparator with open collector outputs<\/td><\/tr>\n<tr><td>74684\t<\/td><td>\t8-bit magnitude comparator<\/td><\/tr>\n<tr><td>74685\t<\/td><td>\t8-bit magnitude comparator with open collector outputs<\/td><\/tr>\n<tr><td>74686\t<\/td><td>\t8-bit magnitude comparator with enable<\/td><\/tr>\n<tr><td>74687\t<\/td><td>\t8-bit magnitude comparator with enable<\/td><\/tr>\n<tr><td>74688\t<\/td><td>\t8-bit equality comparator<\/td><\/tr>\n<tr><td>74689\t<\/td><td>\t8-bit magnitude comparator with open collector outputs<\/td><\/tr>\n<tr><td>74690\t<\/td><td>\tthree-state outputs<\/td><\/tr>\n<tr><td>74691\t<\/td><td>\t4-bit binary counter\/latch\/multiplexer with asynchronous reset, three-state outputs<\/td><\/tr>\n<tr><td>74692\t<\/td><td>\t4-bit decimal counter\/latch\/multiplexer with synchronous reset, three-state outputs<\/td><\/tr>\n<tr><td>74693\t<\/td><td>\t4-bit binary counter\/latch\/multiplexer with synchronous reset, three-state outputs<\/td><\/tr>\n<tr><td>74694\t<\/td><td>\t4-bit decimal counter\/latch\/multiplexer with synchronous and asynchronous resets, three-state outputs<\/td><\/tr>\n<tr><td>74695\t<\/td><td>\t4-bit binary counter\/latch\/multiplexer with synchronous and asynchronous resets, three-state outputs<\/td><\/tr>\n<tr><td>74696\t<\/td><td>\t4-bit decimal counter\/register\/multiplexer with asynchronous reset, three-state outputs<\/td><\/tr>\n<tr><td>74697\t<\/td><td>\t4-bit binary counter\/register\/multiplexer with asynchronous reset, three-state outputs<\/td><\/tr>\n<tr><td>74698\t<\/td><td>\t4-bit decimal counter\/register\/multiplexer with synchronous reset, three-state outputs<\/td><\/tr>\n<tr><td>74699\t<\/td><td>\t4-bit binary counter\/register\/multiplexer with synchronous reset, three-state outputs<\/td><\/tr>\n<tr><td>74716\t<\/td><td>\tprogrammable decade counter<\/td><\/tr>\n<tr><td>74718\t<\/td><td>\tprogrammable binary counter<\/td><\/tr>\n<tr><td>74724\t<\/td><td>\tvoltage controlled multivibrator<\/td><\/tr>\n<tr><td>74740\t<\/td><td>\toctal buffer\/Line driver, inverting, three-state outputs<\/td><\/tr>\n<tr><td>74741\t<\/td><td>\toctal buffer\/Line driver, noninverting, three-state outputs, mixed enable polarity<\/td><\/tr>\n<tr><td>74744\t<\/td><td>\toctal buffer\/Line driver, noninverting, three-state outputs<\/td><\/tr>\n<tr><td>74748\t<\/td><td>\t8 to 3-line priority encoder<\/td><\/tr>\n<tr><td>74779\t<\/td><td>\t8-bit bidirectional binary counter (three-state)<\/td><\/tr>\n<tr><td>74783\t<\/td><td>\tsynchronous address multiplexer<\/td><\/tr>\n<tr><td>74790\t<\/td><td>\terror detection and correction (EDAC)<\/td><\/tr>\n<tr><td>74794\t<\/td><td>\t8-bit register with readback<\/td><\/tr>\n<tr><td>74795\t<\/td><td>\toctal buffer with three-state outputs<\/td><\/tr>\n<tr><td>74796\t<\/td><td>\toctal buffer with three-state outputs<\/td><\/tr>\n<tr><td>74797\t<\/td><td>\toctal buffer with three-state outputs<\/td><\/tr>\n<tr><td>74798\t<\/td><td>\toctal buffer with three-state outputs<\/td><\/tr>\n<tr><td>74804\t<\/td><td>\thex 2-input NAND drivers<\/td><\/tr>\n<tr><td>74805\t<\/td><td>\thex 2-input NOR drivers<\/td><\/tr>\n<tr><td>74808\t<\/td><td>\thex 2-input AND drivers<\/td><\/tr>\n<tr><td>74822\t<\/td><td>\t10-bit bus interface flipflop with three-state outputs<\/td><\/tr>\n<tr><td>74832\t<\/td><td>\thex 2-input OR drivers<\/td><\/tr>\n<tr><td>74848\t<\/td><td>\t8 to 3-line priority encoder with three-state outputs<\/td><\/tr>\n<tr><td>74873\t<\/td><td>\toctal transparent latch<\/td><\/tr>\n<tr><td>74874\t<\/td><td>\toctal d-type flip-flop<\/td><\/tr>\n<tr><td>74876\t<\/td><td>\toctal d-type flip-flop with inverting outputs<\/td><\/tr>\n<tr><td>74878\t<\/td><td>\tdual 4-bit d-type flip-flop with synchronous clear, noninverting three-state outputs<\/td><\/tr>\n<tr><td>74879\t<\/td><td>\tdual 4-bit d-type flip-flop with synchronous clear, inverting three-state outputs<\/td><\/tr>\n<tr><td>74880\t<\/td><td>\toctal transparent latchwith inverting outputs<\/td><\/tr>\n<tr><td>74881\t<\/td><td>\tarithmetic logic unit<\/td><\/tr>\n<tr><td>74882\t<\/td><td>\t32-bit lookahead carry generator<\/td><\/tr>\n<tr><td>74888\t<\/td><td>\t8-bit slice processor<\/td><\/tr>\n<tr><td>74901\t<\/td><td>\thex inverting TTL buffer<\/td><\/tr>\n<tr><td>74902\t<\/td><td>\thex non-inverting TTL buffer<\/td><\/tr>\n<tr><td>74903\t<\/td><td>\thex inverting CMOS buffer<\/td><\/tr>\n<tr><td>74904\t<\/td><td>\thex non-inverting CMOS buffer<\/td><\/tr>\n<tr><td>74905\t<\/td><td>\t12-Bit successive approximation register<\/td><\/tr>\n<tr><td>74906\t<\/td><td>\thex open drain n-channel buffers<\/td><\/tr>\n<tr><td>74907\t<\/td><td>\thex open drain p-channel buffers<\/td><\/tr>\n<tr><td>74908\t<\/td><td>\tdual CMOS 30\u00a0V relay driver<\/td><\/tr>\n<tr><td>74909\t<\/td><td>\tquad voltage comparator<\/td><\/tr>\n<tr><td>74910\t<\/td><td>\t256&#215;1 CMOS static RAM<\/td><\/tr>\n<tr><td>74911\t<\/td><td>\t4 digit expandable display controller<\/td><\/tr>\n<tr><td>74912\t<\/td><td>\t6 digit BCD display controller and driver<\/td><\/tr>\n<tr><td>74914\t<\/td><td>\thex schmitt trigger with extended input voltage<\/td><\/tr>\n<tr><td>74915\t<\/td><td>\tseven segment to BCD decoder<\/td><\/tr>\n<tr><td>74917\t<\/td><td>\t6 digit Hex display controller and driver<\/td><\/tr>\n<tr><td>74918\t<\/td><td>\tdual CMOS 30\u00a0V relay driver<\/td><\/tr>\n<tr><td>74920\t<\/td><td>\t256&#215;4 CMOS static RAM<\/td><\/tr>\n<tr><td>74921\t<\/td><td>\t256&#215;4 CMOS static RAM<\/td><\/tr>\n<tr><td>74922\t<\/td><td>\t16-key encoder<\/td><\/tr>\n<tr><td>74923\t<\/td><td>\t20-key encoder<\/td><\/tr>\n<tr><td>74925\t<\/td><td>\t4-digit counter\/display driver<\/td><\/tr>\n<tr><td>74926\t<\/td><td>\t4-digit counter\/display driver<\/td><\/tr>\n<tr><td>74927\t<\/td><td>\t4-digit counter\/display driver<\/td><\/tr>\n<tr><td>74928\t<\/td><td>\t4-digit counter\/display driver<\/td><\/tr>\n<tr><td>74929\t<\/td><td>\t1024&#215;1 CMOS static RAM<\/td><\/tr>\n<tr><td>74930\t<\/td><td>\t1024&#215;1 CMOS static RAM<\/td><\/tr>\n<tr><td>74932\t<\/td><td>\tphase comparator<\/td><\/tr>\n<tr><td>74933\t<\/td><td>\taddress bus comparator<\/td><\/tr>\n<tr><td>74934\t<\/td><td>\t=ADC0829 ADC, see corresponding NSC datasheet<\/td><\/tr>\n<tr><td>74935\t<\/td><td>\t3.5-digit digital\u00a0voltmeter\u00a0(DVM) support chip for multiplexed 7-segment displays<\/td><\/tr>\n<tr><td>74936\t<\/td><td>\t3.75-digit digital voltmeter (DVM) support chip for multiplexed 7-segment displays<\/td><\/tr>\n<tr><td>74937\t<\/td><td>\t=ADC3511 ADC, see corresponding NSC datasheet<\/td><\/tr>\n<tr><td>74938\t<\/td><td>\t=ADC3711 ADC, see corresponding NSC datasheet<\/td><\/tr>\n<tr><td>74941\t<\/td><td>\toctal bus\/line drivers\/line receivers<\/td><\/tr>\n<tr><td>74945\t<\/td><td>\t4 digit up\/down counter with decoder and driver<\/td><\/tr>\n<tr><td>74947\t<\/td><td>\t4 digit up\/down counter with decoder and driver<\/td><\/tr>\n<tr><td>74948\t<\/td><td>\t=ADC0816 ADC, see corresponding NSC datasheet<\/td><\/tr>\n<tr><td>74949\t<\/td><td>\t=ADC0808 ADC, see corresponding NSC datasheet<\/td><\/tr>\n<tr><td>741005\t<\/td><td>\thex inverting buffer with open-collector output<\/td><\/tr>\n<tr><td>741035\t<\/td><td>\thex noninverting buffers with open-collector outputs<\/td><\/tr>\n<tr><td>742960\t<\/td><td>\terror detection and correction\u00a0(EDAC)<\/td><\/tr>\n<tr><td>742961\t<\/td><td>\tedac bus buffer, inverting<\/td><\/tr>\n<tr><td>742962\t<\/td><td>\tedac bus buffer, noninverting<\/td><\/tr>\n<tr><td>742968\t<\/td><td>\tdynamic memory controller<\/td><\/tr>\n<tr><td>742969\t<\/td><td>\tmemory timing controller for use with\u00a0EDAC<\/td><\/tr>\n<tr><td>742970\t<\/td><td>\tmemory timing controller for use without EDAC<\/td><\/tr>\n<tr><td>744002\t<\/td><td>\tdual 4-input NOR gate<\/td><\/tr>\n<tr><td>744015\t<\/td><td>\tdual 4-bit shift registers<\/td><\/tr>\n<tr><td>744016\t<\/td><td>\tquad bilateral switch<\/td><\/tr>\n<tr><td>744017\t<\/td><td>\t5-stage \u00f710 Johnson counter<\/td><\/tr>\n<tr><td>744020\t<\/td><td>\t14-stage binary counter<\/td><\/tr>\n<tr><td>744024\t<\/td><td>\t7 stage ripple carry binary counter<\/td><\/tr>\n<tr><td>744028\t<\/td><td>\tBCD to decimal decoder<\/td><\/tr>\n<tr><td>744040\t<\/td><td>\t12-stage binary ripple counter<\/td><\/tr>\n<tr><td>744046\t<\/td><td>\tphase-locked loop and voltage-controlled oscillator<\/td><\/tr>\n<tr><td>744049\t<\/td><td>\thex inverting buffer<\/td><\/tr>\n<tr><td>744050\t<\/td><td>\thex buffer\/converter (non-inverting)<\/td><\/tr>\n<tr><td>744051\t<\/td><td>\thigh-speed CMOS 8-channel analog multiplexer\/demultiplexer<\/td><\/tr>\n<tr><td>744052\t<\/td><td>\tdual 4-channel analog multiplexer\/demultiplexers<\/td><\/tr>\n<tr><td>744053\t<\/td><td>\ttriple 2-channel analog multiplexer\/demultiplexers<\/td><\/tr>\n<tr><td>744059\t<\/td><td>\tprogrammable divide-by-N counter<\/td><\/tr>\n<tr><td>744060\t<\/td><td>\t14-stage binary ripple counter with oscillator<\/td><\/tr>\n<tr><td>744066\t<\/td><td>\tquad bilateral switches<\/td><\/tr>\n<tr><td>744067\t<\/td><td>\t16-channel analog multiplexer\/demultiplexer<\/td><\/tr>\n<tr><td>744075\t<\/td><td>\ttriple 3-input OR gate<\/td><\/tr>\n<tr><td>744078\t<\/td><td>\t8-input OR\/NOR gate<\/td><\/tr>\n<tr><td>744094\t<\/td><td>\t8-bit three-state shift register\/latch<\/td><\/tr>\n<tr><td>744316\t<\/td><td>\tquad analog switch<\/td><\/tr>\n<tr><td>744351\t<\/td><td>\t8-channel analog multiplexer\/demultiplexer with latch<\/td><\/tr>\n<tr><td>744353\t<\/td><td>\tTriple 2-channel analog multiplexer\/demultiplexer with latch<\/td><\/tr>\n<tr><td>744511\t<\/td><td>\tBCD to 7-segment decoder<\/td><\/tr>\n<tr><td>744514\t<\/td><td>\t4-to-16 line decoder\/demultiplexer with input latches<\/td><\/tr>\n<tr><td>744520\t<\/td><td>\tdual 4-bit synchronous binary counter<\/td><\/tr>\n<tr><td>744538\t<\/td><td>\tdual retriggerable precision monostable multivibrator<\/td><\/tr>\n<tr><td>747007\t<\/td><td>\thex buffer<\/td><\/tr>\n<tr><td>747266\t<\/td><td>\tquad 2-input XNOR gate<\/td><\/tr>\n<tr><td>7429841\t<\/td><td>\t10-bit bus-interface D-type latch with three-state outputs<\/td><\/tr>\n<tr><td>7440103\t<\/td><td>\tpresettable 8-bit synchronous down counter<\/td><\/tr>\n<tr><td>7440105\t<\/td><td>\t4-bit by 16-word FIFO register<\/td><\/tr>\n<\/table>\n\n\n\n<p><\/p>\n","protected":false},"excerpt":{"rendered":"<p>This is a table with an overview of all TTL IC typenumbers and a short description of the chip. The chips are available in many variants such as LS and HC types, the operation is the same, but the electrical specifications are different. You cannot simply replace an LS with an HC type without being [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":2873,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[48],"tags":[128,124,129,85],"class_list":["post-4568","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-eng","tag-description","tag-ic","tag-list","tag-ttl"],"_links":{"self":[{"href":"https:\/\/www.heinpragt.nl\/index.php?rest_route=\/wp\/v2\/posts\/4568","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.heinpragt.nl\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.heinpragt.nl\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.heinpragt.nl\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.heinpragt.nl\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=4568"}],"version-history":[{"count":2,"href":"https:\/\/www.heinpragt.nl\/index.php?rest_route=\/wp\/v2\/posts\/4568\/revisions"}],"predecessor-version":[{"id":4570,"href":"https:\/\/www.heinpragt.nl\/index.php?rest_route=\/wp\/v2\/posts\/4568\/revisions\/4570"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.heinpragt.nl\/index.php?rest_route=\/wp\/v2\/media\/2873"}],"wp:attachment":[{"href":"https:\/\/www.heinpragt.nl\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=4568"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.heinpragt.nl\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=4568"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.heinpragt.nl\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=4568"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}